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Board Technical Description
6. Multi-Gigabit Transceiver Data Ports [4:7] - J2 10GE Base-CX4 Connector
Board FPGA multi-gigabit transceiver Data Ports 4 through 7 are wired to a 10GE Base-
CX4 connector J2 on the XM104. The four data port connections between the XM104 FMC
HPC connector and the 10G Base-CX4 connector J2 are defined in Table 1-7 .
Table 1-7:
FPGA Multi-Gigabit Transceiver Data Ports 4 - 7 Connectivity
FMC HPC
Connector J1 Pin
A14
A15
A18
A19
B16
B17
B12
B13
Signal Name
DP4_M2C_P (1)
DP4_M2C_N (1)
DP5_M2C_P (1)
DP5_M2C_N (1)
DP6_M2C_P (1)
DP6_M2C_N (1)
DP7_M2C_P (1)
DP7_M2C_N (1)
J2 Connector Pin
(Receiver)
S1
S2
S3
S4
S5
S6
S7
S8
FMC HPC
Connector J1 Pin
B33
B32
B37
B36
A39
A38
A35
A34
Signal Name
DP7_C2M_N
DP7_C2M_P
DP6_C2M_N
DP6_C2M_P
DP5_C2M_N
DP5_C2M_P
DP4_C2M_N
DP4_C2M_P
J2 Connector Pin
(Transmitter)
S9
S10
S11
S12
S13
S14
S15
S16
Notes:
1. All receiver signals are AC coupled using 0.1 uF series capacitors
7. 2 Kb EEPROM
An STMicroelectronics M24C02 2 Kb serial IIC bus EEPROM component provides a small
amount of non-volatile memory storage on the XM104. The IIC interface is connected
directly to the board’s IIC interface as shown in Figure 1-2, page 10 .
The IIC address of this component is controlled by a combination of the board’s interface
and chip enable connections to the component inputs on the XM104. Signals GA0 and GA1
from the board are connected to the chip enable inputs of the M24C02 component enables
E0 and E1. Xilinx boards provide GA0 and GA1 signal strapping to 3.3V and GND signals
creating different E0 and E1 chip enable decodes on the E1 and E0 inputs of the EEPROM.
The IIC memory addressing protocol requires a bus master to initiate communication to a
peripheral device using a start condition followed by a device select code. The device select
code consists of a 4 bit Device Type Identifier and a 3-bit Chip Enable Address (E2, E1 and
E0). Bit 0 is used to indicate read/write. The Device Type Identifier for the EEPROM is 1010
binary. Table 1-8 defines the generic EEPROM Device Select Code as well as specific Device
Code Select addresses of the EEPROM when the XM104 is connected to a Xilinx board
defined in Table 1-1, page 7 .
Table 1-8:
EEPROM IIC Device Select Code
Bit 7:4 Device
Type Identifier
1010
Bit 3
0
Bit 2
GA0
Bit 1
GA1
Bit 0 LSB
Read/Write
Description
Connected to mezzanine FMC HPC
interface
The M24C02 component data sheet is available online at www.st.com .
FMC XM104 Connectivity Card User Guide
UG536 (v1.1) September 24, 2010
www.xilinx.com
15
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